Some OSs use this approach to implement a generic high precision timer service, where the local APIC count is set to a value that depends on which event will happen soonest. For example, during task switches an OS could set the count to a value that depends on the new task's priority (so that some tasks run for a small amount of time and other tasks run for a larger amount of time), and there wouldn't be any unwanted IRQs.
Apimac timer fullscreen hotkey software#
The advantage of this mode is that software can have precise control over when timer IRQs occur. Instead, software has to set a new count each time if it wants more timer IRQs. The current count is decremented at a rate that depends on the CPU's external frequency ("bus frequency") divided by the value in the local APIC's "Divide Configuration Register".įor example, for a 2.4 GHz CPU with an external/bus frequency of 800 MHz, if the Divide Configuration Register is set to "divide by 4" and the initial count is set to 123456 then the local APIC timer would decrement the count at a rate of 200 MHz and generate a timer IRQ every 617.28 us, giving a rate of IRQs of 1620.01 Hz.įor one-shot mode, the local APIC decrements the current count (and generates a timer IRQ when the count reaches zero) in the same way as in periodic mode however it doesn't reset the current count to the initial count when the current count reaches zero. In this way the local APIC generates IRQs at a fixed rate depending on the initial count. The local APIC decrements the current count until it reaches zero, then generates a timer IRQ and resets the current count to the initial count and begins decrementing the current count again. The third mode (TSC-Deadline mode) is an extension that is only supported on recent CPUs.įor periodic mode, software sets a "initial count" and the local APIC uses it for a "current count". The first 2 modes (periodic and one-shot) are supported by all local APICs.
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